1. Technical Field
This invention relates generally to memory devices, and more particularly, to a memory array incorporating resistive memory cells.
2. Background Art
Generally, memory devices associated with computers and other electronic devices are employed to store and maintain information for the operation thereof. Typically, such a memory device includes an array of memory cells, wherein each memory cell can be accessed for programming, erasing, and reading thereof. Each memory cell maintains information in an “off” state or an “on” state, also referred to as “0” and “1” respectively, which can be read during the reading step of that memory cell.
As such electronic devices continue to be developed and improved, the amount of information required to be stored and maintained continues to increase. FIG. 1 illustrates a type of memory cell known as a nanoscale resistive memory cell 30, which includes advantageous characteristics for meeting these needs. The memory cell 30 includes, for example, a Cu electrode 32, a superionic layer 34 such as Cu2S on the electrode 32, an active layer 36 such as Cu2O or various polymers on the Cu2S layer 34, and a Ti electrode 38 on the active layer 36. Initially, assuming that the memory cell 30 is unprogrammed, in order to program the memory cell 30, a negative voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory cell 30 from a higher to a lower potential in the direction from electrode 32 to electrode 38 (see FIG. 2, a plot of memory cell current vs. electrical potential applied across the memory cell 30). This potential is sufficient to cause copper ions to be attracted from the superionic layer 34 toward the electrode 38 and into the active layer 36, causing the active layer 36 (and the overall memory cell 30) to be in a low-resistance or conductive state (A). Upon removal of such potential (B), the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory cell 30) remain in a conductive or low-resistance state.
In order to erase the memory cell (FIG. 2), a positive voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory cell 30 from a higher to a lower electrical potential in the reverse direction. This potential causes current to flow through the memory cell in the reverse direction (C), and is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34, in turn causing the active layer 36 (and the overall memory cell 30) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory cell 30.
FIG. 2 also illustrates the read step of the memory cell 30 in its programmed (conductive) state and in its erased (nonconductive) state. An electrical potential Vr (the “read” electrical potential) is applied across the memory cell 30 from a higher to a lower electrical potential in the same direction as the electrical potential Vpg. This electrical potential is less than the electrical potential Vpg applied across the memory cell 30 for programming (see above). In this situation, if the memory cell 30 is programmed, the memory cell 30 will readily conduct current (level L1), indicating that the memory cell 30 is in its programmed state. If the memory cell 30 is erased, the memory cell 30 will not conduct current (level L2), indicating that the memory cell 30 is in its erased state.
FIGS. 3, 4 and 5 illustrate a memory cell array 40 which incorporates memory cells 30 of the type described above. As illustrated in FIG. 3, the memory cell array 40 includes a first plurality 42 of parallel conductors (bit lines) BL0, BL1, . . . BLn, and a second plurality 44 of parallel conductors (word lines) WL0, WL1, . . . WLn overlying and spaced from, orthogonal to, and crossing the first plurality of conductors 42. A plurality of memory cells 30 of the type described above are included, each associated with a select diode 50 having a (forward) threshold Vt and a (reverse) breakdown voltage Vb, to form a memory cell-diode structure. Each memory cell 30 is connected in series with a select diode 50 between a conductor BL of the first plurality 42 thereof and a conductor WL of the second plurality 44 thereof at the intersection of those conductors, with the diode 50 oriented in a forward direction from the conductor BL of the first plurality 42 thereof to the conductor WL of the second plurality 44 thereof. For example, as shown in FIG. 3, memory cell 3000 and diode 5000 in series connect conductor BL0 of the first plurality of conductors 42 with conductor WL0 of the second plurality of conductors 44 at the intersection of those conductors BL0, WL0, memory cell 3010 and diode 5010 in series connect conductor BL1 of the first plurality of conductors 42 with conductor WL0 of the second plurality of conductors 44 at the intersection of those conductors BL1, WL0, etc.
In order to program a selected memory cell (FIG. 3), for example selected memory cell 3000, the voltage applied to the conductor BL0 is selected as (Vpg+Vt) greater than the voltage (0) applied to the conductor WL0, where Vpg is as defined above and Vt=(forward) threshold voltage of diode 5000. Additionally, this same voltage Vpg+Vt is applied to each of the conductors WL1, . . . WLn, and zero voltage is applied to each of the conductors BL1, . . . BLn. This results in zero potential being applied across each of the memory cell-diode structures (other than the selected memory cell 3000 and diode 5000 structure) connected to the conductor BL0 and the conductor WL0. Each of the other memory cell-diode structures has applied thereacross, from higher to lower potential in the reverse direction of the diode 50, an electrical potential which is equal to Vpg+Vt. This electrical potential is less than the breakdown voltage Vb of the diode 50, and thus no current flows through the associated memory cell. Thus, the incorporation of the diodes 50 allows one to properly select and program a memory cell, without disturbing any of the other memory cells in the array.
In order to erase a selected memory cell (FIG. 4), for example selected memory cell 3000, the voltage applied to the conductor WL0 is (Ver+Vb) greater than the voltage (0) applied to the conductor BL0, where Ver is as defined above and Vb=(reverse) breakdown voltage of diode 5000. Additionally, a voltage of for example 0.5(Vpg+Vt) is applied to each of the conductors WL1, . . . WLn, and each of the conductors BL1, . . . BLn. This results a potential of 0.5(Vpg+Vt) being applied across each of the diode-memory cell structures (other than the selected memory cell 3000 and diode 5000 structure) connected to the conductor BL0 and the conductor WL0, from higher to lower potential in the reverse direction of the diode 50. This electrical potential 0.5(Vpg+Vt) is less than the breakdown voltage Vb of the diode 50, and thus no current will flow through the associated memory cell. Each of the other memory cell-diode structures has applied thereacross an electrical potential of zero. Similar to the above, the incorporation of the diodes 50 allows one to properly select and erase a memory cell, without disturbing any of the other memory cells in the array.
In order to read a selected memory cell (FIG. 5), for example selected memory cell 3000, the voltage applied to the conductor BL0 is (Vr+Vt) greater than the voltage (0) applied to the conductor WL0, where Vr is as defined above and Vt=threshold voltage of diode 5000). Additionally, a voltage of Vr+Vt is applied to each of the conductors WL1, . . . WLn, and zero voltage is applied to each of the conductors BL1, . . . BLn. This results in zero potential applied across each of the memory cell-diode structures (other than the selected memory cell 3000 and diode 5000 structure) connected to the conductor BL1 and WL0. Each of the other memory cell-diode structures has applied thereacross, from higher to lower potential in the reverse direction of the diode 50, an electrical potential which is equal to Vr+Vt. This potential Vr+Vt is less than the breakdown voltage of the diode 50, so that no current passes through the associated memory cell. Thus, the incorporation of the diodes 50 allows one to properly select and read a memory cell, without disturbing or otherwise influencing any of the other memory cells in the array.
FIG. 6 illustrates ideal (G) and actual (H) voltage-current characteristics for a diode of the type incorporated in the memory array of FIGS. 3–5. It is to be noted that in order to achieve erasing of a selected memory cell, current must be conducted through the selected memory cell, and in order to achieve this conduction of current, the diode associated therewith must be in breakdown. Ideally, such a diode would have a low threshold voltage (forward direction of the diode) on the order of 0.6 volts, and a low breakdown voltage (reverse direction of the diode) on the order of 2.0 volts, as these voltages would readily allow rapid and effective programming, reading, erasing of a selected cell with relatively low electrical potentials applied thereto, so that a low potential power supply can be used.
However, in reality, while a typical diode may indeed have a threshold voltage on then order of 0.6 volts, the breakdown voltage is substantially greater than 2.0 volts (illustrated at in FIG. 6), i.e., for example, 4.5 volts or substantially more. This leads to problems in achieving breakdown of the diode, which is essential in erasing the associated memory cell as described above.
Therefore, what is needed is an approach wherein the ideal characteristics described above are achieved.